- 母鐘；時鐘脈沖；主脈沖
- 母鍾
- 直鐘
- 主時鐘
- 主鐘
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master clock中文什么意思
例句與用法
- Time service ; concepts and terms of master clocks
報時業(yè)務(wù).母鐘的概念和術(shù)語 - Master clock , microprocessor
微處理機主時鐘 - Master clock frequency
主時鐘頻率 - Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains . the data transaction protocol comes from the most basic work way of uart . when the master clock is 16 . 7mhz , the pcm side and adpcm side clocks both are 2 . 38mhz , the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14 . 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14 . 7 us
在主時鐘為16 . 7mhz ， pcm數(shù)據(jù)端與adpcm數(shù)據(jù)端時鐘均為2 . 38mhz時，模擬結(jié)果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發(fā)送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發(fā)送器的最大延遲為14 . 7 s ，設(shè)計時盡可能的使編碼與解碼的時間相差不多，從結(jié)果看出基本達到這個要求。